The present invention relates to a programmable counter system of the swallow operation type.
A configuration of a programmable counter system of the swallow operation type is illustrated in FIG. 1. A frequency division factor of a prescaler 1 is set at "M+1" or "M" according to the logic level "1" or "0" of a frequency division factor select signal SW. A pulse input fin at the input is frequency-divided by the frequency division factor "M+1" or "M". In this instance, for simplicity, a pulse output fout from the prescaler 1 is supplied to two programmable downcounters A and B. In this specification, symbols denoting signals, for example, fin and fout, will also be used to designate their frequencies. An output Pout1 of the counter A and an output Pout2 of the counter B are applied to a flip-flop 2, which serves as a control circuit for a frequency division factor select signal SW. The output signals then invert the logical level of the flip-flop 2. The output signal of the flip-flop 2 is applied as the select signal SW to the prescaler 1.
Assume now that the select signal SW is logical "1" and the frequency division factor of the prescaler 1 is "M+1". In this condition, the prescaler 1 frequency-divides the input signal fin by the frequency division factor "M+1" to produce an output signal fout at a frequency fin/(M+1). The output signal fout is input to the counters A and B. Values N1 and N2 (N2 being larger than N1) have been previously set in the counters A and B, respectively. The counters A and B count down the output signal fout. Since N1 is smaller than N2, as mentioned above, the counter A completes the counting operation earlier than the counter B. When the output signal Pout1 of the counter A is logical "1", the output signal of the flip-flop 2 is inverted in logical level, so that the select signal SW applied to the prescaler 1 is switched from logical "1" to logical "0". When the select signal SW is switched to logical "0", the frequency division factor is switched from "M+1" to "M". Therefore, the output signal fout from the prescaler 1 has a frequency fin/M. The counter B counts down the output signal fout (=fin/M). The counter B had already completed the frequency division of "N1". Therefore, when the counter B completes the frequency division of "N2-N1", the output signal Pout2 of the counter B is logical "1". The output signal Pout2 is input as a preset signal to the counters A and B, and also to the flip-flop 2. In response to this preset signal, the preset values N1 and N2 are set in the counters A and B, and the select signal SW is logical "1", and the frequency division factor "M+1" is set in the prescaler 1. Thus, the programmable counter system returns to the original or initial state. Subsequently, an operation similar to the above is repeated.
In the above operation, a division number N, which is a reciprocal of a frequency division factor of an overall programmable counter system shown in FIG. 1, i.e., a ratio of the frequency fin of the input signal to that, f.sub.preset, of the preset signal, is given as: ##EQU1## In equation (1), when M=10, EQU N=10N2+N1.
Note here that if the first place of numerals in BCD (binary coded decimals) is allotted to N1 and the second and subsequent places of the numerals to N2, the circuit of FIG. 1 serves as a BCD programmable counter system. Further, since the counter of FIG. 1 is of the swallow operation type, it is sufficient that the counters A and B merely count the output signal at the frequency fin/M+1 of fout/M. Therefore, high speed operation is not required for this counter system.
A counting example where N=259, M=10, N1 =9 and N2=25, will now be described.
FIG. 2 illustrates a practical arrangement of a prescaler which performs the frequency division of the input signal fin at a frequency division factor 10 (=M) when SW=logical "0", and at 11 (=M+1) when SW=logical "1". As shown, the prescaler 1 comprises dynamic type flip-flop 11.sub.0 to 11.sub.3, inverters 12 and 13, an OR circuit 14, an AND circuit 15, and a NOR circuit 16. FIGS. 3A to 3E and FIGS. 4A to 4E illustrate waveforms at the various portions when the select signal SW is "0" and "1", respectively. More specifically, FIG. 3A illustrates a waveform of the input signal fin, and FIGS. 3B to 3E show waveforms of the output signals Q0 to Q3 of the flip-flop 11.sub.0 to 11.sub.2. Similarly, FIG. 4A shows a waveform of the input signal fin, and FIGS. 4B to 4E show waveforms of the output signals Q0 to Q3 of the flip-flop 11.sub.0 to 11.sub.3. As seen from FIGS. 3A to 3E, when the select signal SW is logical "0", the input frequency fin is divided by a factor of ten through a decimal change 1.fwdarw.3.fwdarw.14.fwdarw.12.fwdarw.8.fwdarw.9 .fwdarw.11.fwdarw.6.fwdarw.4.fwdarw.0. Similarly, as seen from FIGS. 4A to 4E, when SW="1", the input frequency fin is divided by a factor of eleven through a decimal change of 1.fwdarw.3 .fwdarw.15.fwdarw.14.fwdarw.12.fwdarw.8.fwdarw.9.fwdarw.11.fwdarw.6.fwdarw .4.fwdarw.0.
FIGS. 5 shows a practical arrangement of the combination of the counters A and B or a counter section. The counter A is composed of flip-flop 21.sub.0 to 21.sub.3 of the dynamic type and inverters 22 and 23, and AND gates 24, 25 and 26. The counter B is composed of flip-flops 21.sub.4 to 21.sub.11 of the dynamic type, inverters 27 and 28, and AND gates 29 to 34. Assume now that 259 is set in these counters A and B in BCD form. A decimal number "9" is set as NI in the counter A in BCD form. That is, preset data PD0="1", PD1="0", PD2="0" and PD3="1" are combined to represent a decimal number 9 and are set in the flip-flops 21.sub.0 to 21.sub.3, respectively. Numerals 2 and 5 in the second and third places of the number 259 are preset as N2 in the counter B. To this end, preset data PD4="1", PD5="0", PD6="1", and PD7="0", which together denote a decimal number 5, are set in the flip-flops 21.sub.4 to 21.sub.7, respectively. Preset data PD8="0", PD9="1", PD10="0" and PD11=" 0", which together denote a decimal number 2, are set into the flip-flops 21.sub.8 to 21.sub.11, respectively. In the same way, N.sub.2 =25 is set in the counter B in BCD.
FIGS. 6A to 6Q are timing charts of waveforms at various portions in the circuit of FIG. 5. The character 60 is not used to avoid confusion with the number 60. FIG. 6A shows a waveform of an input signal CPin input to the counters A and B, i.e., the output signal fout of the prescaler 1 in FIG. 1. FIGS. 6B to 6E show output signals Q0 to Q3 of the flip-flops 21.sub.0 to 21.sub.3 in the counter A. FIG. 6F is a waveform of an output signal from the counter A. FIGS. 6G to 6N are waveforms of the output signals Q4 to Q11 of the flip-flops 21.sub.4 to 21.sub.11, respectively. FIGS. 6P is a waveform of an output signal f.sub.preset of the counter B, and FIG. 6Q is a waveform of a flip-flop 2 as a select signal control circuit. As seen from FIGS. 6A to 6Q, an output signal at a frequency fin/259 is obtained by counting the factor-of-11 output signal from the prescaler 1 nine times and counting the factor-of-10 output signal from the same sixteen times (16=25-9).
The example shown in FIG. 5 uses decimal operation type counters. Another example using binary operation type counters will be described referring to FIG. 7. In this example, the 4-bit type counter A is composed of four dynamic type flip-flops with preset functions 41.sub.0 to 41.sub.3, an inverter 42, and AND gates 43 to 45. The 6-bit type counter B is composed of six dynamic counters with preset functions 41.sub.4 to 41.sub.9, and AND gates 46 to 50. When the counters A and B are of the binary operation type, the prescaler used has a frequency division factor selectable from "2.sup.n +1" and "2.sup.n "(where n is the number of bits of the counter A). In the example shown in FIG. 7, the counter A must be of the type in which the frequency division factor is selectable from (2.sup.4 +1) =17 and 2.sup.4 =16. In the counter A, N1 as the preset value (division number) of the lower order is programmed in BCD form. N2 as the preset value (division number) of the higher order is programmed in the counter B. When the counters A and B are thus programmed, the programming counter system in FIG. 7 contains the following frequency division number preset: ##EQU2##
When N1=7 and N2=30, N2=30, N=16.times.30+7 =487. For programming N1=7 in the counter A, programming data PD0="1", PD1="1", PD2="1", PD3="0" are set in the flip-flops 41.sub.0 to 41.sub.3. For programming N2=30 in the counter B, programming data PD4="0", PD5="1", PD6="1", PD7="1", PD8="1" and PD9="0" are set in the flip-flops 41.sub.4 to 41.sub.9, respectively.
FIGS. 8A to 8M are waveforms of signals at various portions in the counter circuit shown in FIG. 7. FIG. 8A shows a waveform of an input signal PCin applied to the counters A and B shown in FIG. 1. FIGS. 8B to 8E show waveforms of output signals Q0 to Q3 from the flip-flops 41.sub.0 to 41.sub.3, respectively. FIG. 8F shows a waveform of an output signal from the counter A. FIGS. 8G to 8L are waveforms of output signals Q4 to Q9 of the flip-flops 41.sub.4 to 41.sub.9 of the counter B, respectively. FIG. 8M is a waveform of an output signal preset of the counter B. FIG. 8N shows a waveform of an output signal SW of the flip-flop 2 constituting a select signal control circuit. As seen from FIGS. 8A to 8N, ##EQU3## The result is equal to the value obtained by the equation (2).
As described above, when a programmable counter system of swallow operation type uses binary counters, a prescaler must have a frequency division factor selectable from 2.sup.n +1 and 2.sup.n for the counter A of n bit length in which the lower order bit of the frequency division factor are preset. The prescaler must be one bit larger than the counter A which stores the lower order bits. The prescaler is a circuit operating at high speed, and hence its power dissipation per bit is large. Further, the increased number of bits in the prescaler is accompanied by an increase in the number of control circuits, resulting in damage to the control circuit. Therefore, it is necessary to limit the number of bits in the prescaler.